A multi-phase clock scheme relieves clock speed requirements in circuits that require high speed clocking. In a typical multi-phase clock scheme, delayed versions of a clock (e.g., a video clock employed for transmitting video data over a serial link) are generated (each delayed version of the clock having a different phase) and the delayed versions are employed with the clock itself.
The expression “multi-phase clock set” is used herein to denote a set of L clocks, each having frequency fdck and each having a different phase φm that satisfies φm=φoffset+2π(m/L)+Δm where the index “m” is a non-negative integer in the range {0, . . . , L−1}, and Δφm is an error term. Typically Δφm is much smaller than the phase increment 2π/L, and a multi-phase clock set is generated to approximate (as closely as is practical) an ideal multi-phase clock set consisting of L clocks, each having frequency fdck and each having a different phase φm=φoffset+2π(m/L). In typical applications, a multi-phase clock set is generated in response to a principal clock having frequency fdck and phase φoffset (in other typical applications, the principal clock has frequency other than fdck). Typically, a transmitter uses a multi-phase clock set to transmit (to a receiver) data (having a data rate greater than the frequency fdck) together with one clock of the multi-phase clock set (or another clock). The receiver generates a second multi-phase clock set in response to the received clock, and recovers the data using the second multi-phase clock set.
For example, in systems implementing the conventional Digital Video Interface (“DVI link”) adopted by the Digital Display Working Group, a video clock having frequency fvclk is generated and transmitted over a serial link to a receiver. Both the transmitter and receiver include circuitry for generating a multi-phase clock set in response to the video clock. One multi-phase clock set is employed in the transmitter to transmit data with a data rate greater than the video clock frequency fvclk; the other multi-phase clock set is employed by the receiver to recover the data.
Typically, the phase differences between different pairs of clocks of a multi- phase clock set differ from clock pair to clock pair. Specifically, the phase difference between any two of the clocks satisfies φm−φn=2π(m−n)/L+Δφmn, where m·n, and the error term Δφmn typically differs from clock pair to clock pair. If N pairs of clock pairs are considered, the quantity (m−n) has the same predetermined value for all clock pairs, and N error term differences (Δφmn)i−(Δφmn)j=(φm−φn)i−(φm−φn)j are measured, where each index i identifies one of the clock pairs and each index j identifies another of the clock pairs, then the error term differences (Δφmn)i−(Δφmn)j over all (or some) of the pairs of clock pairs provide a measure of the uniformity of the clock phases of the multi-phase clock set. For example, the sum (or average) of the absolute values of the error term differences (Δφmn)i−(Δφmn)j over all (or some) of the pairs of clock pairs is one indication of the uniformity of the clock phases of the multi- phase clock set, and the difference between the largest and the smallest of the error term differences (Δφmn)i−(Δφmn)j is another indication of the uniformity of the clock phases of the multi-phase clock set.
The uniformity of the phases of the clocks of a multi-phase clock set becomes critical as the data rate increases (and can be significant even at low data rates). However, measuring the clock phase uniformity in the time domain requires a very high-speed measurement for serial links when the data rate is high (i.e., when the clock frequency is high and/or the ideal phase difference between clocks is small). Thus, it is typically not feasible for automatic test equipment (ATE) to measure clock phase uniformity in the time domain.